Flip-flops are used in many applications and, in particular, in digital systems, such as processors, digital signal processors and memories. FIG. 1 shows a circuit diagram of a prior art D flip-flop 10. The D flip-flop 10 has a data sensing block 12 coupled to an SR latch 14. The data sensing block 12 is well-known. A substantially similar data sensing block is described in U.S. Pat. No. 4,910,713 to Madden et al.
Typically, the SR latch 14 has a pair of cross-coupled NAND gates 16, 18. One input of one NAND gate 16 has a set input S that receives a set signal, and one input of the other NAND gate 18 has a reset input R that receives a reset signal. The SR latch 14 outputs two signals, Q and Q. A high voltage level, a logical one, on the set input S and a low voltage level, a logical zero, on the reset input R will reset (clear) the flip-flop 14 such that the Q output has a low voltage level and the Q output has a high voltage level. A high voltage level on the reset input R and a low voltage level on the set input S will set the SR latch 14 to a state in which the Q output has a high voltage level and the Q output has a low voltage level. The SR latch 14 operates on the assumption that a low voltage level will not appear simultaneously at both the set S and reset R inputs. If both the set S and reset R inputs have a high voltage level, the SR latch 14 will not change state, but remain in its present state. A high voltage level on the set S and reset R inputs is considered nonactivating. The SR latch 14 can also be formed with cross-coupled NOR gates.
Referring also to FIG. 2, a timing diagram of the data sensing block 12 and SR latch 14 of FIG. 1 is shown. When the clock (clk) signal is at a low voltage, the set S and reset R outputs of the data sensing block 12 are at a high voltage level. When the clock signal (clk) transitions high, the D input is at a low voltage and the D inputis at a high voltage; therefore the set S signal remains at a high voltage level while the reset R signal transitions to a low voltage level as shown by arrow 21. In response to the low voltage level of the reset R signal at the NAND gate 18 input, the Q signal transitions to a high voltage level, as shown by arrow 22. In response to the high voltage level of the S and Q signals at the NAND gate 16 inputs, the Q signal transitions to a low voltage level (arrow 23).
Note that the delay of the NAND gate 18 determines the amount of time for the Q signal to transition from a low voltage level to a high voltage level (arrow 24) and the delay of the NAND gate 16 determines the amount of time for the Q signal to transition from the high voltage level to a low voltage level (arrow 25).
When the D inputis at a high voltage level and the D inputis at a low voltage level and the clock signal (clk) transitions high, the NAND gates 16 and 18 also determine the amount of time for the Q and Q signals to transition to a high voltage level and a low voltage level, respectively.
The inventors identified that the cross-coupled NAND gates 16, 18 of the SR latch 14 limit the speed of the D flip-flop 10. The cross-coupled NAND gates 16, 18 are a single stage which simultaneously generates and latches the Q and Q signals. When either the set or reset signal transitions from a high to a low voltage level, the set S and reset R signals must pass through two NAND gates 16, 18 to generate the Q and Q outputs. Therefore the SR latch 14 has two gate delays between a change of the voltage level on the set S or reset R inputs and the rising and falling edges at the Q and Q outputs. This degrades the speed of the circuit by more than 70%. Moreover, at the process limits, the speed further degrades and the amount of speed degradation can exceed 100%.
In FIG. 3, a similar circuit 20 to the circuit shown in FIG. 1 is used in another prior art D flip-flop. The circuit 20 of FIG. 3 is similar to the circuit 10 of FIG. 1 except that the transistor N6 (FIG. 1) is not used. Transistor N6 ensures the static operation of the data sensing block 12 of the flip-flop 10 for low-power applications. Transistor N6 does not have significant impact on the speed of the flip-flop 10. Since the SR latch 14 of FIG. 3 is the same as the SR latch 14 of FIG. 1, the D flip-flop 20 of FIG. 2 has similar performance problems to the D flip-flop of FIG. 1.
Processor speed and performance is ever-increasing. Therefore a flip-flop that operates at a higher speed is desirable.